Novel multiplier architecture is proposed based on the concept of memory-based computing in contrast to logic computations, thus making it efficient to implement both on Application Specific Integrated Circuits (ASICs) or Field Programmable Gate Array (FPGAs). Unlike the traditional approaches of using column bits compressors/ counters for partial product reduction, in this work, the partial products are added using basic ’m-operand adders’ where m= 2, 3, 4, 5. This reduces the depth of pipelining that result in long carry propagation. These adders are designed using only registers and small ROMs and optimized the performance w.r.t. area and delay. The Partial product generator used is an AND gate-array for unsigned multiplier, and for signed multiplier radix-4 Booth encoding is used. The architecture can be extended to ’N-bit multipliers’ by re-use of basic m-operand adder modules. The proposed unsigned multiplier utilizes 15.52% less LUTs and 41.033% less delay compared to existing 16-bit multiplier [1]. The proposed 16-bit signed multiplier has 36.17% less LUTs but 5.5% of more delay than that of existing 16-bit multiplier [2] respectively. After exhaustive experimentation and analysis made by varying the bit-length and number of operands it’s evident that proposed multiplier outperforms existing ones.