The designing of low power circuits has been a constant area of research in integrated circuits. As the technology advances, the electronic systems are becoming battery operated hence the efficient utilization of power is necessary because of limited power sources. In computers, the memory requirement is unavoidable, so flip-flops are used as digital data storage unit. Flip-Flops are sequential circuits whose response is controlled by the clock signal. While studying the internal circuitry of the flip-flops we can observe that the power dissipation depends mostly on the switching activity of the circuit due to clock signal. Here we have proposed a reset-abled flip-flop which is fast in performance, has low power dissipation at high data activity and requires less area on silicon chip. Flip-Flop finds numerous applications like counters, shift registers, memory elements etc. Here we have proposed an UP-DOWN counter using gate diffusion input (GDI) cell, its performance is evaluated and compared with conventional method-based counters. The circuits are simulated in standard 90 nm CMOS process technology in Cadence Virtuoso EDA tool. The performance analysis of the proposed flip-flop at 400 MHz clock frequency shows that the power dissipation is 187.1 nW, signal propagation delay is 127.15 ps and area requirement is 81.8 μm2. Also, at 1 GHz clock frequency, the proposed counter dissipates 1040.55 nW power and it requires 388.2 μm2 area on IC chip.