In this paper, a variable-length conditional counter algorithm is proposed to count or add the partial products of serial multiplier circuits for minimizing computational delay. The proposed variable-length conditional counter enables optimizing critical path delay and improving its slack time at different input frequencies. The evaluation of the slack time of any circuit is essential to estimate the highest frequency of operation. In this work, the slack time of the proposed architecture is computed and compared with the related work. The result shows that slack time is higher as compared to the existing circuit, which implies that the proposed architecture of the serial multiplier operates at high frequency. The proposed variable-length conditional counter design and its serial multiplier architecture of 8, 16, 32 and 64-bit has been designed using Verilog HDL. The simulation of the proposed design has been done on the mentor Graphics EDA Tool. The physical layout design of the proposed 8-bit multiplier circuit using 180-nm CMOS technology is obtained in this work.