As CMOS technology shrinks to the deep submicron range, increased power dissipation becomes a big issue. Due to its non-volatility, fast speed, great durability, CMOS compatibility, and low power consumption, the Spin transfer torque (STT) switching mechanism based on Magnetic tunnel Junction (MTJ) is widely regarded as one of the most promising spintronic devices for the post-CMOS era. The research presented here proposes a novel Arithmetic Logic Unit (ALU) that makes use of Spin Hall Effect (SHE) to aid with STT/ MTJ. In this study, we use SHE-assisted STT logic to create a Hybrid Full Adder and three other logics (AND, OR, and XOR). The proposed logics are then used to create an adder circuit, which is used to create an Arithmetic Logic Unit (ALU). A comparison of each of the proposed designs to the DPT L − C2MOS − ALU and P-MALU has been performed. The simulation findings show that the proposed designs outperform competing ALU designs, with a 28% reduction in power consumption and a corresponding reduction in latency. For circuit simulation in 45nm technology, the Cadence Virtuoso tool is employed.